The present invention relates to a semiconductor device, and more particularly to a semiconductor device employing an SOI (Silicon On Insulator) substrate.
With an increase in need for low electric power consumption and high operation speed on semiconductor integration circuits, it has been strongly demanded that respective semiconductor devices are miniaturized and their operation voltages are decreased. In light of this demand, SOI-type semiconductor devices attract attention, in place of conventional Bulk-type semiconductor devices. The SOI-type devices employ an SOI substrate having a semiconductor layer and an insulating layer stacked one on the other, while the Bulk-type devices employ a substrate entirely formed of a semiconductor layer. As compared with the Bulk-type devices, the SOI-type devices are considered to have several advantages, such as a smaller parasitic capacitance, a steeper sub-threshold characteristic, and a smaller substrate-bias effect.
An explanation will be given on a typical structure and manufacturing method of SOI-type devices, with reference to FIGS. 13A and 13B, which are plan and cross-sectional views showing an SOI-type MISFET.
As shown in FIGS. 13A and 13B, the SOI-type MISFET has a silicon (Si) support layer 12 and a single-crystal silicon (Si) active layer 16 stacked one on the other through an insulating film 14 of a silicon oxide film (SiO.sub.2). A source region 24 and a drain region 26 are arranged in the active layer 16 to interpose a channel region 22. The source region 24 and the drain region 26 are formed by doping the active layer 16 with an impurity having a conductivity type opposite to that of the channel region 22 by means of, e.g., ion-implantation. A gate electrode 34 is disposed on the channel region 22 through a gate insulating film 32 of a silicon oxide film (SiO.sub.2).
The insulating film 14 makes it difficult to control the electric potential of the body section in the SOI-type device, while the electric potential of a body section can be easily controlled in the Bulk-type devices. Consequently, the electric potential of the body section falls in a floating state during device operation in the SOI-type device, thereby bringing about problems, such that the device threshold voltage varies during the device operation, and the device breakdown voltage becomes lower. In light of these problems, various kinds of attempts have been made to control the electric potential of the body section of the SOI-type devices , as in the Bulk-type devices.
FIGS. 14A and 14B are plan and cross-sectional views showing a Bulk-type MISFET. FIGS. 15A and 15B are plan and cross-sectional views showing a thin-film SOI-type MISFET having a typical structure for controlling the body electric potential.
The Bulk-type MISFET shown in FIGS. 14A and 14B has a Si substrate 116, a gate insulating film 132, a gate electrode 134, a channel region 122, a source region 124, and a drain region 126. The gate electrode 134 is disposed on the Si substrate 116 through the thin gate insulating film 132. For example, in the Bulk-type MISFET, the Si substrate 116 is doped with an impurity to form a conductive layer having a low resistivity, by which the electric potential of the channel region 122a is controlled.
The thin-film SOI-type MISFET shown in FIGS. 15A and 15B has a Si support layer 212 and a Si active layer 216 stacked one on the other through an insulating film 214. A source region 224 and a drain region 226 are arranged in the active layer 216 to interpose a channel region 222. The source region 224 and the drain region 226 have a conductivity type opposite to that of the channel region 222. A gate electrode 234 is disposed on the channel region 222 through a gate insulating film 232.
In the thin-film SOI-type MISFET, the insulating film 214 is interposed between the Si support layer 212 and the Si active layer 216. For this reason, it is necessary to form a contact region (body-contact region) to efficiently control the body electric potential of each device.
The thin-film SOI-type MISFET shown in FIGS. 15A and 15B has a contact region 228 (body-contact region) having a conductivity type the same as that of the channel region 222. The gate electrode 234 has, e.g., a T-shape to form the contact region 228 and separate it from the source region 224 and the drain region 226. The body-contact region 228 is formed by doping the active layer 216 with an impurity at a high concentration to lower the resistivity of part of the active layer 216.
In the thin-film SOI-type MISFET shown in FIGS. 15A and 15B, in addition to the main channel region 222 formed under a portion 234a of the gate electrode 234, an additional channel region 223 is formed under a portion 234b of the gate electrode 234 to have a conductivity type the same as that of the main channel region 222. The additional channel region 223 brings about a parasitic MIS capacitor 240 as well as hardly contributing to the current drivability of the device. Where the parasitic capacitance of the device remarkably increases due to the parasitic MIS capacitor 240, problems arise in that the device comes to have a low operation speed and a large electric power consumption. Further, where the body-contact region having a low resistivity and the additional channel region 223 are located adjacent to each other, another problem arises in that junction leakage current increases.